S912XEP100BMAG

The S912XEP100BMAG is a 16-bit Microcontroller based on enhanced HCS12X CPU with CISC architecture operates at a maximum frequency of 50MHz. The device incorporates 1000kB internal flash, 64kB internal RAM, 4kB EEPROM, 12-channel 24-bit A/D converter and 119 general-purpose I/O pins. This device also features peripherals like two inter-integrated circuit (IIC) bus module, one CAN 2.0 A, B software compatible module, eight serial communications interface (SCI) and three serial peripheral interface modules (SPI).

• Upward compatible with MC9S12 instruction set
• Enhanced indexed addressing
• Access to large data segments independent of PPAGE
• Interrupt module (INT)
• Module mapping control (MMC)
• Debug module
• Background debug mode (BDM)
• Memory protection unit (MPU)
• Low power loop control pierce oscillator utilizing a 4MHz to 16MHz crystal
• Internally filtered, frequency modulated phase-locked-loop clock generation (IPLL)
• Clock and reset generation (CRG)
• COP watchdog
• Real time interrupt
• Clock monitor
• Fast wake up from STOP in self clock mode
• Enhanced capture timer (ECT) - 8 x 16-bit channels for input capture or output compare
• Standard timer module (TIM) - 8 x 16-bit channels for input capture or output compare
• Periodic interrupt timer (PIT)
• 8 PWM (pulse-width modulator) channels
• On-chip voltage regulator - two parallel, linear voltage regulators with bandgap reference
• Low-voltage detect (LVD) with low-voltage interrupt (LVI)
• Power-on reset (POR) circuit
• Low-voltage reset (LVR)
• Low-power wake-up timer (API)
• Hysteresis and configurable pull up/pull down device on all input pins

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