IS43TR16640CL-125JBLI

IS43TR16640CL-125JBLI is a 1600MT/s 1Gb 64Mx16 DDR3 SDRAM. The memory controller initiates Levelling mode of all DRAMs by setting bit 7 of MR1 to 1. When entering write levelling mode, the DQ pins are in undefined driving mode. During write levelling mode, only NOP or DESELECT commands are allowed, as well as an MRS command to exit write levelling mode. Since the controller levels one rank at a time, the output of other ranks must be disabled by setting MR1 bit A12 to 1. The controller may drive DQS low and DQS# high after a delay of tWLDQSEN, at which time the DRAM has applied on-die termination on these signals. After tDQSL and tWLMRD, the controller provides a single DQS, DQS# edge which is used by the DRAM to sample CK - CK# driven from controller. tWLMRD(max) timing is controller dependent.

• Standard voltage is VDD and VDDQ = 1.5V ± 0.075V
• High speed data transfer rates with system frequency up to 1066cMHz
• 8 internal banks for concurrent operation, 8n-bit pre-fetch architecture
• Programmable CAS latency, programmable additive latency: 0, CL-1, CL-2
• Programmable CAS WRITE latency (CWL) based on tCK, BL switch on the fly
• Programmable burst sequence: sequential or interleave, asynchronous RESET pin
• Auto self refresh (ASR), self refresh temperature (SRT), partial array self refresh
• OCD (off-chip driver impedance adjustment), dynamic ODT (on-die termination)
• Write levelling, up to 200MHz in DLL off mode
• 96-ball BGA package, industrial temperature rating range from -40°C ≤ TC ≤ 95°C