MT40A2G8SA-062E IT:F

MT40A2G8SA-062E IT:F is a DDR4 SDRAM. It is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

• VDD = VDDQ = 1.2V±60mV, 1.2V pseudo open-drain I/O
• On-die, internal, adjustable VREFDQ generation, command/address (CA) parity
• 16 internal banks (x4, x8): 4 groups of 4 banks each, 8 internal banks (x16): 2 groups of 4 banks
• 8n-bit prefetch architecture, programmable data strobe preambles
• Data strobe preamble training, command/address latency, write levelling
• Multipurpose register READ and WRITE capability, self refresh mode, Per-DRAM addressability
• Low-power auto self refresh (LPASR), temperature controlled refresh (TCR)
• Fine granularity refresh, self refresh abort, maximum power saving, output driver calibration
• Nominal, park, and dynamic on-die termination (ODT), data bus inversion (DBI) for data bus
• 78-ball FBGA package, industrial operating temperature range from -40≤ TC≤ 95°C