HEF4024BP

The HEF4024BP is a 7-stage Binary Ripple Counter with a clock input (CP/), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the high to low transition of CP\. A high on MR clears all counter stages and forces all outputs low, independent of CP\. Each counter stage is a static toggle flip-flop. It operates over a recommended VDD power supply range of 3 to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS or another input.

• Tolerant of slow clock rise and fall time
• Fully static operation
• Standardized symmetrical output characteristics
• Complies with JEDEC standard JESD 13-B

Приложения

Medical, Industrial, Consumer Electronics, Automation & Process Control