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74VHCT573AFT(BJ) is a CMOS digital silicon monolithic IC. It is an advanced high speed CMOS octal latch with 3-state output fabricated with silicon gate C²MOS technology. It achieves the high speed operation similar to equivalent bipolar schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (active-low OE). When the active-low OE input is high, the eight outputs are in a high impedance state. The input voltage is compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3V to 5V system. Input protection and output circuit ensure that 0 to 5.5V can be applied to the input and output pins without regard to the supply voltage. This structure prevents device destruction due to mismatched supply and input/output voltages such as battery back-up, hot board insertion, etc.
- Octal D-type latch with 3-state outputs, AEC-Q100 qualified (Rev. H)
- Low power dissipation ICC is 4.0µA (max) at Ta = 25°C
- Compatible with TTL inputs: VIL = 0.8V (max), VIH = 2.0V (min)
- Power down protection is provided on all inputs and outputs
- Balanced propagation delay is tPLH ≈ tPHL, supply voltage range from 4.5V to 5.5V
- Pin and function compatible with the 74 series (74ACT/HCT/AHCT etc.) 573 type
- Quiescent supply current is 4µA max at (VIN = VCC or GND, 5.5V, Ta = 25°C)
- Propagation delay time (LE-Q) is 7.7ns typ at (5.0 ±0.5V, CL=15pF, Ta=25°C, input: tr=tf=3ns)
- Operating temperature range from -40°C to 125°C
- TSSOP20B package
Технически характеристики
0
Tri State
8mA
TSSOP-B
4.5V
8bit
0
125°C
-
To Be Advised
D Type
7.7ns
TSSOP-B
20Pins
5.5V
74VHC
-40°C
AEC-Q100
AEC-Q100
Технически документи (1)
Законодателство и околна среда
Страна, в която е реализиран последният важен производствен процесСтрана на произход:Japan
Страна, в която е реализиран последният важен производствен процес
RoHS
RoHS
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